1. Field of the Invention
The present invention relates to a memory system including a circuit for controlling accesses to a bank of memories to which interleaved access is applied and an information processing system into which the memory system is incorporated.
2. Description of the Prior Art
As an information processing speed has been increased according to higher performance of the MPU (Micro Processing Unit) in the information processing system, a higher speed of the memory system has been requested. However, there is a limit to such higher speed of the memory system. Further, if the large number of high speed memory systems should be employed, cost of the overall system is increased because of high cost of the high speed memory system.
Therefore, there has been a memory system which employs such an approach that the memory system is constructed as a multi-bank system in which a plurality of independently accessible memories are installed and the interleaved access to the memory system is performed by accessing respective banks on a time-division base, so that the memory system can be accessed apparently quicker than the access time of the memories constituting respective banks if such memory system is observed externally. For example, the information processing system containing the memory system consisting of multi-bank DRAMs (Dynamic Random Access Memories) will be discussed herein. As shown in a timing chart of the interleaved access of FIG. 1, in the case that a cycle time of the DRAM is about 80 (ns) and a cycle time of the MPU is about 5 (ns), data can be supplied from the memory system constructed as a sixteen-bank system to the MPU every cycle of the MPU by performing the interleaved access to such memory system. As a result, an apparent access time of the DRAM can be reduced.
Under the premise such that individual accesses should be applied to different banks in successive accesses to the memory system respectively and the interleaved access is always carried out, the above-mentioned advantage can be achieved.
However, the accesses to the memory system have not always been performed by using the above addresses, and thus the case has happened where the accesses to the same bank should be performed successively. In such case, non-interleaved access has been inevitably performed and thus succeeding memory accesses have been kept in their waiting states until the cycle time of the preceding memory access has been terminated. As a result, an access efficiency has been lowered or degraded.
As explained above, in the prior art, according to the memory system constructed as the multi-bank system to which interleaved access is applied, the expected advantage can be achieved if the interleaved access to the memory system can be performed. In contrast, if the non-interleaved accesses to the same bank are carried out successively, the memory system has not been able to be utilized to reduce apparently the access time of the memories. Therefore, the memory system in the prior art has had such a disadvantage that the access efficiency is lowered or degraded.